1) Field of the Invention
This invention relates generally to a process of planarizing insulating layers in semiconductor devices and more particularly to a process for removing planarized insulating layers over alignment mark areas.
2) Description of the Prior Art
Photolithography and planarization processes are two very important processes in the manufacture of advanced semiconductor devices. One photolithography tool used extensively is a stepper, such as an ASM lithography stepper. A stepper projects an image on a wafer to expose a photoresist pattern. The image size is only a portion of the substrate, such as the size of an individual chip. The stepper must move the image from chip to chip on the substrate to expose all of the chips. Steppers have automated alignment systems that use alignment marks on the substrate to align to for each exposure.
A substrate contains both alignment mark areas and device areas. FIG. 2B shows an alignment mark area 10 and device areas 20 (chip areas, product areas) on a wafer 14. FIG. 1 shows an example of an alignment mark area 10 on a substrate which has an alignment mark patterns 12A. The alignment mark patterns in the alignment mark area 20 are formed of a pattern of lines 12A. The alignment marks are often formed by etching patterns in to the silicon substrate. The alignment marks 12B are positioned strategically around the wafer and used by the stepper machines to align to various parts of the wafer. Also, FIG. 2A shows a top down view of device area 20 having conductive lines 12B.
Another key process in semiconductor manufacturing is planarization. Planarization is the smoothing or leveling of a surface, typically a surface of an insulating layer. Many insulating layers at least partially follow the topography of the underlying layers. The planarization process shapes the insulating layer back to a flat planar level. This level layer improves yields by improving photo processes and metal structures (layers) formed over the smooth planarized layer.
Planarization can be performed by several different methods, such as chemical mechanical polishing (CMP), spin-on-glass (SOG) or photoresist etchback. Chemical mechanical polishing is becoming more popular as it is a controllable process that produces an uniform level layer.
The inventors have experienced a problem when using the planarization process with insulating layers over alignment mark areas. Steppers have not be able to identify the alignment marks in alignment mark areas where the insulating layer over the alignment marks have been planarized especially using a chemical mechanical polish processes.
Therefore, there is a need to develop a process to planarize insulating layers over alignment mark areas so that the stepper can recognize/read the alignment marks.
Workers in the art have worked extensively with planarization processes. U.S. Pat. No. 5,393,233 (Hong) teaches a double poly process for forming a buried bit line ROM. The patent shows a typical planarization by chemical-mechanical polishing (CMP) to achieve a self aligned double poly word line structure. U.S. Pat. No. 5,456,756 (Chan et al.) teaches a clamp that prevents metal from depositing over alignment mark areas. However, the patent does not address the problem of viewing the alignment marks through subsequent overlying planarized layers.